Abstract:Thispresentation provides a holistic understanding of all aspects of reliability failure mechanisms of an advanced IC product. It covers wafer, die, and package and board level reliability issues. Part I address all major reliability issues from the IC product design prospective and part II for the end users to evaluate the reliability of the ICs they will use in their system. This presentation is suitable to teachers and students interested in Microelectronics, IC and package designers, quality and reliability engineers and the component engineers.

Biography:

Dr. Richard RAO is currently a Fellow of Microsemi Corp, a lead supplier of high reliability integrate circuit, located in southern California, USA and an elected Senior Member of IEEE.  He is responsible for the corporate reliability and advanced packaging solutions. His focus is to find the advanced packages to meet the high performance, high reliability and high power semiconductor ICs; to study the new failure modes and mechanisms of cutting edge Silicon and packaging technologies as well as to develop design for reliability solutions for advanced circuits, packaging and chip to package interaction. He has a Ph.D. degree in solid mechanics of materials from the University of Science and Technology of China. Prior to joining Microsemi in 2004, Dr. Rao held various academic and technical positions in reliability physics and engineering. He was an associate professor at University of Science and Technology of China, a research fellow at Northwestern University, Evanston, IL, USA and a NSTB Research Fellow of Singapore. He also held senior and principal technical positions in Motorola Electronics and Ericsson Inc. He has published over 30 papers on reliability physics and applications and also a main contributor of several JEDEC standards. He is a technical committee member of IRPS (International Reliability and Physics Symposium) and ECTC (Electronics Component and Technology Conference). He is a frequent speaker to IRPS, ECTC, ISQED (International Symposium on Quality Electronics Design), ASME Symposiums and a keynote speaker to ICEPT and International Conf on System on Chip, etc. Dr. Rao has over 20 years’ hands on experience and knowledge in silicon to package to system integration such as HKMG and FinFET, high performance FCBGA/CSP, FOWLP,2.5D/3D, silicon photonics, chip to package to board interaction, board and system level reliability physics and applications. He has conducted professional development courses on advanced IC reliability to both industrial and academic worlds.